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In computing, DDR3 SDRAM, an abbreviation for double data rate type three synchronous dynamic random-access memory, is a modern type of dynamic random-access memory (DRAM) with a high bandwidth ("double data rate") interface, and has been in use since 2007. It is the higher-speed successor to DDR and DDR2 and predecessor to DDR4 synchronous dynamic random-access memory (SDRAM) chips. DDR3 SDRAM is neither forward nor backward compatible with any earlier type of random-access memory (RAM) because of different signaling voltages, timings, and other factors. DDR3 is a DRAM interface specification. The actual DRAM arrays that store the data are similar to earlier types, with similar performance. The primary benefit of DDR3 SDRAM over its immediate predecessor, DDR2 SDRAM, is its ability to transfer data at twice the rate (eight times the speed of its internal memory arrays), enabling higher bandwidth or peak data rates. With two transfers per cycle of a quadrupled clock signal, a 64-bit wide DDR3 module may achieve a transfer rate of up to 64 times the memory clock speed megahertz (MHz) in megabytes per second (MB/s). With data being transferred 64 bits at a time per memory module, DDR3 SDRAM gives a transfer rate of (memory clock rate) × 4 (for bus clock multiplier) × 2 (for data rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus with a memory clock frequency of 100 MHz, DDR3 SDRAM gives a maximum transfer rate of 6400 MB/s. The DDR3 standard permits DRAM chip capacities of up to 8 gibibits, and up to 4 ranks of 64 bits each for a total maximum of 16GiB per DDR3 DIMM. Because of a hardware limitation, first addressed in Ivy Bridge-E in 2013, most Intel CPUs only support up to 4 gibibit modules for 8GiB DIMMs. All AMD CPUs correctly support the full spec for 16GiB DDR3 DIMMs. ==Overview== Compared to DDR2 memory, DDR3 memory uses 30% less power. This reduction comes from the difference in supply voltages: 1.8 V or 2.5 V for DDR2, and 1.5 V or 1.35 V for DDR3. The 1.5 V supply voltage works well with the 90 nanometer fabrication technology used in the original DDR3 chips. Some manufacturers further propose using "dual-gate" transistors to reduce leakage of current. According to JEDEC, 1.575 volts should be considered the absolute maximum when memory stability is the foremost consideration, such as in servers or other mission-critical devices. In addition, JEDEC states that memory modules must withstand up to 1.80 volts before incurring permanent damage, although they are not required to function correctly at that level〔. Another benefit is its prefetch buffer, which is 8-burst-deep. In contrast, the prefetch buffer of DDR2 is 4-burst-deep, and the prefetch buffer of DDR is 2-burst-deep. This advantage is an enabling technology in DDR3's transfer speed. DDR3 modules can transfer data at a rate of 800–2133 MT/s using both rising and falling edges of a 400–1066 MHz I/O clock. This is twice DDR2's data transfer rates (400–1066 MT/s using a 200–533 MHz I/O clock) and four times the rate of DDR (200–400 MT/s using a 100–200 MHz I/O clock). High-performance graphics was an initial driver of such bandwidth requirements, where high bandwidth data transfer between framebuffers is required. Because the hertz is a measure of ''cycles'' per second, and no signal cycles more often than every other transfer, describing the transfer rate in units of MHz is technically incorrect, although very common. It is also misleading because various memory timings are given in units of clock cycles, which are half the speed of data transfers. DDR3 does use the same electric signaling standard as DDR and DDR2, Stub Series Terminated Logic, albeit at different timings and voltages. Specifically, DDR3 uses SSTL_15.〔Jaci Chang ''Design Considerations for the DDR3 Memory Sub-system''. Jedex, 2004, p. 4. http://www.jedex.org/images/pdf/samsung%20-%20jaci_chang.pdf〕 DDR3 prototypes were announced in early 2005. Products in the form of motherboards appeared on the market in June 2007 based on Intel's P35 "Bearlake" chipset with DIMMs at bandwidths up to DDR3-1600 (PC3-12800). The Intel Core i7, released in November 2008, connects directly to memory rather than via a chipset. The Core i7 supports only DDR3. AMD's first socket AM3 Phenom II X4 processors, released in February 2009, were their first to support DDR3. DDR3 DIMMs have 240 pins and are electrically incompatible with DDR2. A key notch—located differently in DDR2 and DDR3 DIMMs—prevents accidentally interchanging them. Not only are they keyed differently, but DDR2 has rounded notches on the side and the DDR3 modules have square notches on the side. 〔(【引用サイトリンク】author="DocMemory" )〕 DDR3 SO-DIMMs have 204 pins. For the Skylake microarchitecture, Intel has also designed a SO-DIMM package named UniDIMM, which can use either DDR3 or DDR4 chips. The CPU's integrated memory controller can then work with either. The purpose of UniDIMMs is to handle the transition from DDR3 to DDR4, where pricing and availability may make it desirable to switch RAM type. UniDIMMs have the same dimensions and number of pins as regular DDR4 SO-DIMMs, but the notch is placed differently to avoid accidentally using in an incompatible DDR4 SO-DIMM socket.〔http://www.techpowerup.com/205231/how-intel-plans-to-transition-between-ddr3-and-ddr4-for-the-mainstream.html〕 GDDR3 memory, sometimes incorrectly referred to as "DDR3" because of its similar name, is an entirely different technology, as it is designed for use in graphics cards and is based on DDR2 SDRAM. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「DDR3 SDRAM」の詳細全文を読む スポンサード リンク
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